30 Millionth avast! Home Edition User Registered

Prague – 11th May 2007: For Immediate Release: ALWIL Software a.s. is extremely proud to announce another milestone in the number of avast®! antivirus Home Edition registrations has been reached with the registration, today, of the 30 millionth (30,000,000) user

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FORTUNE Magazine Again Ranks AMD as the Industry’s Most Admired Company for Innovation

For 38 years, AMD has been a driving force behind innovation and advancement in the semiconductor industry. We are passionate about connecting with our customers, understanding their needs, and bringing them the most innovative products and solutions.

We are honored that, for the second year in a row, FORTUNE magazine ranked AMD as the Most Admired company in the semiconductor industry for Innovation and the fourth Most Admired semiconductor company overall.

Latest Intel processor could steal the ISSCC show

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SAN FRANCISCO — Intel Corp. will come to the International Solid-State Circuits Conference this week with tips for reining in runaway power as chip integration rises, following up on the call to arms it sounded at last year’s ISSCC. Intel technology executives last week briefed analysts on techniques applied in the McKinley processor architecture as well as on such speculative technologies as body biasing and a new nonvolatile memory that could displace flash in cell phones and other space-constrained portables.

“Once a geek, always a geek,” Pat Gelsinger, Intel’s chief technology officer, joked as he described the topics Intel would broach at the conference. Gelsinger’s keynote address last year had warned that Moore’s Law would not only advance silicon integration but also bring on exponential increases in power consumption. In addition to biasing techniques that achieve faster clocks and higher yields with lower voltage levels, Intel’s technologists previewed a processor that would integrate 291 million transistors.

That device, code-named McKinley, has been sampling since last February and is slated to enter production around midyear, said Intel fellow John Crawford, director of the McKinley architecture project. Intel and co-developer Hewlett-Packard Co. will jointly present six papers at ISSCC, most of them revolving around McKinley’s cache and circuit designs. The 3-Mbit Level 3 cache, for example, achieves 85 percent efficiency (compared with 70 percent for traditional cache designs) while consuming 20 percent less silicon area.

The 64-Gbits/second L2 cache bandwidth is up to 4x greater than that of proprietary RISC processors. The L1 cache — the one closest to the core — has a one-cycle latency that provides a 15 to 25 percent performance increase over typical, two- to three-cycle-latency designs. Elimination of load delay penalties simplifies compiler scheduling, Crawford said.

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